Time interval comparison system

ABSTRACT

Apparatus for comparing a recorded, standard interval of time with subsequent intervals of time and determining whether such subsequent intervals are equal to the standard interval to within a predetermined degree of accuracy measured as a fraction of the standard interval. The invention includes means to record a standard interval of time as an electrical condition, means to record a subsequent interval of time as a second electrical condition, and time-controlled means to compare the two conditions to determine which is the longer and by how much. One embodiment of the invention includes a timing circuit with a digitally controlled time constant to indicate the discrepancy between a subsequent interval and the standard interval for different standard intervals. Another embodiment uses an additional time recorder to make a direct comparison between the record of the standard interval and a record of the discrepancy interval.

United States Patent [72] Inventor Bruce H. Kamens 56 Hotchkiss Ave.,Thomaston, Conn. 06787 [21] Appl. No. 799,368 [22] Filed Feb. 14, 1969[45] Patented Feb. 16, 1971 [54] TIME INTERVAL COMPARISON SYSTEM 11Claims, 5 Drawing Figs.

[52] US. Cl 307/232, 307/293, 307/295; 328/134, 328/129 [51] Int. ClH03k 5/20 [50] Field ol'Search 307/232,233,293,295;328/133',134,141,155,129-131; 329/126; 324/83 (D), 68 (C)[56] References Cited UNITED STATES PATENTS 2,897,363 7/1959 Gorgas328/133 3,296,525 1/1967 Sakuma 307/232X 3,349,400 l0/l967 AsheretalABSTRACT: Apparatus for comparing a recorded, standard interval of timewith subsequent intervals of time and determining whether suchsubsequent intervals are equal to the standard interval to within apredetermined degree of accuracy measured as a fraction of the standardinterval. The invention includes means to record a standard interval oftime as an electrical condition, means to record a subsequent intervalof time as a second electrical condition, and time-controlled means tocompare the two conditions to determine which is the longer and by howmuch. One embodiment of the invention includes a timing circuit with adigitally controlled time constant to indicate the discrepancy between asubsequent interval and the standard interval for different standardintervals. Another embodiment uses an additional time recorder to make adirect comparison between the record of the standard interval and arecord of the discrepancy interval.

TIME INTERVAL COMPARISON SYSTEM This invention relates to electricaltiming apparatus and particularly to apparatus for measuring an intervalof time and determining the amount by which it differs from a standardinterval in terms expressed as a fraction of the standard interval.

In the measurement of physical data where a certain event is supposed tooccur within a certain predetermined interval of time in order, forexample, to maintain the quality of a manufactured product at asatisfactory level, it is sometimes sufficient, and even desirable,merely to determine how long it took the event to occur and to comparethis length of time with a standard length of time that the event wassupposed to take, instead of making a direct,'possibly destructiveanalysis of the quality of-the product. The difference between the timeactually taken and the standard interval of time supposed to have beentaken may then be compared with the standard interval to express thedifference as a fraction of the standard interval. If the standardinterval is known, the calculation of the fraction may not be difficult,but if the standard interval is arbitrarily chosen and differs from timeto time, the calculation of the fraction becomes more complicated.

Time can be recorded in an electrical circuit in terms of a voltage orcurrent that begins at a predetermined level and changes in apredetermined way, for example, by increasing linearly, throughout theinterval to be measured. The final value of the voltage or current isthen, ideally, a function only of time as the sole variable, but in factthe final value of the voltage or current is also affected by otherfactors that should be constant but may actually be variables, such asthe initial value and the circuit parameters that determine the rate ofchange. It is preferable, therefore, to record an interval of time, andparticularly a standard interval to which reference may be made againand again, as a circuit condition that, as nearly as possible, dependsonly on time. A shift register that steps in uniform increments inresponse to pulses of fixed repetition rate is such a circuit since theaccuracy of the recorded time depends almost exclusively on the accuracyof the pulse generator. By using the same pulse generator to record astandard interval on one shift register and to record a subsequentinterval on a second, similar shift register, and by comparing the finalconditions of the two shift registers, the accuracy of comparison isincreased still more and is then subject only to the drift error of thepulse generator.

The circuit condition of a shift register that consists of a chain offlip-flop circuits is identified by the state of conductivity of theflip-flops. A flip-flop is a circuit having two stable states ofconductivity, and at any time it will be either in its first state orits second state. An actuating pulse of the proper polarity applied toactuating signal input terminals will cause the flip-flop to change fromits first to its second state, and the next actuating pulse will causeit to change back to its first state. By using the pulse derived fromeach flip-flop as it changes from its second to its first state as theactuating signal for the next flip-flop in the chain, and by providing achain having a sufficiently large number of flip-flops, any desiredinterval may be recorded, and identified, in terms of whether eachindividual flip-flop in the chain is in its first or its second state ofconductivity.

ln the language of logic as applied to such circuits, the first statemay be identified as a 1, or a condition in which the output of aparticular section of the flip-flop is high, and the second state may beidentified as a 0, or a condition in which the output is low." Theidentifications are, to some extent, arbitrarily selected, but oneapplied to a given circuit must be followed in setting up the completesystem. Thus, the record of an interval of time may be a series of lsand 0's along a chain of flip-flops or along a chain of whateverelements make up the shift register. Because of the fact that theelements of the shift register are stable in either state, the record oftheinof coincidence circuits to compare the state of each element of thefirst shift register with a corresponding element of the second shiftregister. If the two shift registers have identical series of ls and0's, the subsequent interval of time is the same as the standardinterval, and this information may be utilized in any desired way, afterwhich the second shift register may be brought back to its originalcondition to await a signal to record yet another interval of time.

The invention includes means to determine how great the discrepancy isbetween the subsequent interval and the standard interval in those casesin which there is a discrepancy. One embodiment" for doing this utilizesa sawtooth wave generator, or timing circuit having time constantelements or impedances controlled by the shift register that measuresthe standard interval. A long standard interval would result in one timeconstant; a shorter standard interval would result in a different timeconstant. For a period of time equal to the discrepancy the timingcircuit is energized and continuously increasing signal is produced byit. An indicator, which may include a trigger circuit, is set at acertain value of signal level, which is arbitrarily chosen to correspondto apredetermined fraction of the standard interval. The uniformlyincreasing signal is applied to the indicator and the indicator is soarranged as to be actuated if the discrepancy period is equal to orgreater than the predetermined fraction of the standard interval.Further circuits may be included to show whether the subsequentintervalis shorter or longer than the standard interval.

Another way of indication whether or not the discrepancy intervalexceeds a predetermined fraction of the standard interval is to providea third shift register and a second set of coincidence circuits thatmeasui'es, element by element, the coincidence circuits that measures,element by element, the coincidence of the elements of the third shiftregister with those of the first shift register. For a period of timeequal to the discrepancy interval the third shift register is energizedwith pulses having a repetition rate that is a known multiple of therepetition rate of the pulse signal that energized the first shiftregister. For example, if the third shift register is energized withpulses that have a repetition rate l00 times the repetition rate of thepulses that energized the first shift register, and if, during thediscrepancy interval, coincidence is achieved between each element ofthe first shift register and the corresponding element of the thirdshift register, it will be because the discrepancy interval is at least1 percent of the standard interval. lf the repetition rate of pulsesapplied to the third shift register is only ten times that ofthe pulsesapplied to the first shift register, coincidence during the discrepancyinterval will indicate that the discrepancy is at least l0 percent ofthe standard interval. ln general, coincidence during the discrepancyinterval when the third shift register is actuated by pulses having arepetition rate N times that of the pulses applied to the first shiftregister will indicate that the discrepancy interval is at least equalto UN times the standard interval.

The invention also includes means to control the actuation of the shiftregisters and to start the measurement of the discrepancy interval,either at the end of the subsequent interval or at a time after thebeginning of the subsequent interval equal to the standard interval,whichever occurs first. If the subsequent interval is shorter than thestandard interval, the discrepancy interval will start with the end ofthe subsequent interval and will terminate at a time corresponding tothe end of the standard interval, but if the subsequent interval islonger that the standard interval the discrepancy interval will start ata time corresponding to the end of the standard interval and willterminate at the end of the subsequent interval.

The invention will be described in greater detail in the followingspecification together with the drawings in which:

FIG. 1 is a circuit diagram, partially in schematic and partially inblock lo'gic form, of shift registers, coincidence circuits, and atiming circuit in a timing system according to the invention;

FIG. 2 is a block diagram oflogic circuits connected to control and toutilizeinformation in conjunction with the circuit in FIG. 1;

FIG. 3 is a timing diagram of pulse signals produced in the 1 operationof the circuits in FIGS. 1 and 2 FIG. 4 is a schematic diagram of acircuit for indicating whether a particular intervalof time measured bythe circuits of FIGS. 1 and 2 has substantially the same length as astandard interval or is shorter or longer than the standard interval;

and

FIG. 5 is a block diagram of a modified portion of the circuit in FIG.1.

The circuit in FIG. 1 comprises a pulse oscillator 11 that produces apulse signal 12 having a predetermined repetition rate. The oscillator11 is connected to an amplifier 13, the output signal 14 of whichcorresponds to an inverted replica of the pulse signal 12. The amplifier13 is connected to the toggle input terminal 15 of the shift register 16that comprises a series of flip-flops 17-27. The amplifier 13 is alsoconnected to a NOR gate 28 which receives a-second signal from a source29 to be described hereinafter. The output'of the NOR gate 28 is'connected to an amplifier 31 and from there to the toggle input 30 of ashift register 32 that comprises a chain of flipflops 33-43. Todistinguish the two shift registers, the shift register 32 may bereferred to as a storage registerin which information is stored as tothe length of the standard interval of time and the shift register 16may be referred to as a counter, or counter-timer, in which informationis stored as to the duration of a subsequent interval of time to becompared with the standard interval.

A set of coincidence circuits 46-56 is connected to the counter 16 andto the storage register 32 so that each element of the counter and acorresponding element of the storage register is connected to a specificone of the coincidence circuits.

The illustrations of the flip-flops in both the counter and the storageregister areconventional, and all of them can be identical. In additionto the toggle input terminal 15, each flipflop has a reset terminal, andfirst and second output terminals converse to each other. The resetterminal for the flip-flop 17 is indicated by reference numeral 58 andthe output terminals of the flip-flop 17 are indicated'by referencenumerals 59-60. The reset terminal of the flip-flop 33 is indicated byreference numeral 61, and the output terminals of the flip-flop 33 areindicated by reference numerals 62 and 63, respectively. The signal atthe terminal 62 is always the converse of the signal at the terminal 63;i.e. when the signal at the terminal 62 is high, that at terminal 63 islow, and vice versa.

Each of the identical coincidence circuits 46-56 comprises three NORgates, but only the coincidence circuit 46 that connects the flip-flops17 and 33 is shown in detail. This circuit comprises a first NOR gate 64having a first input terminal 65 connected to one output terminal 60 ofthe flip-flop 17 and a second input terminal 66 connected to one outputterminal 63 of the flip-flop 33. The coincidence circuit also includes asecond NOR gate 67 having a first input terminal 68 connected to theoutput terminal 59 and a second input terminal 69 connected to theconverse output terminal 62. The third NOR gate 70 in the coincidencecircuit 46 has a first input terminal 71 connected to the outputterminal 72 of the NOR gate 64 and a second input terminal 73 connectedto the output terminal 74 of the NOR gate 67. The output terminal 75 ofthe NOR gate is also the output terminal of the first coincidencecircuit 46.

v The means shown in FIG. 1 for comparing a discrepancy interval withthe standard interval to determine whether or not the discrepancy islarger than a predetermined fraction of the standard interval includes acircuit for generating a continuously increasing voltage in the natureof a sawtooth wave. This circuit includes an impedance 76, which, in thepresent embodiment, is a resistor, which is adjustable to set thetolerance to a desired value, and a group of capacitors 77-87 that maybe switched into operative connection with the resistor 76 by acorresponding group of individual transistor switches 88-98. The baseelectrode of each of the transistors 88-98 is connected to one outputterminal of the flip-flops 33-43, respectively, to connect selectedonesof the capacitors 77-87 in operative series connection with the resistor76 depending on which of the flip-flops 33-43 are in their 1" state,i.e. the state that applies a voltage to corresponding ones of thetransistors 88-98 to render them conductive. The resistor 76 and theoperative ones of the capacitors 77 -87 constitute the time constantparameters of the timing circuit.

Separate diodes 99-109 are connected directly in parallel with theemitter-collector output circuit of the transistors 88- -98,respectively, and are polarized to provide quick discharge of any of thecapacitors 77-87 that may be charged in the operation of the circuit. Acontrol transistor 110 is connected between the common terminal 111 anda line 112, which is the common junction of the resistor 76 with all ofthe capacitors 77-87; The transistor 110 is controlled by a signal 113applied to the input terminal 114 to make the transistor nonconductivefor the duration of this signal and allow the operative ones of thecapacitors 77 -87 to charge through the resistor 76 at a rate determinedby the time constant of this timing circuit.

A trigger circuit comprising a pair of transistors 115 and 116 isconnected in parallel with the output circuit of the transistor 110 andin parallel with the capacitors 77-87 and the switching tranistors'88-98 to be triggered when the voltage on the line 112 reaches a certainlevel. The transistors 115 and 116 are arranged so that the collectorelectrode of each is directly connected to the base electrode of theother, and a load impedance 117 is connected in series with the emitterelectrode of the transistor 116. The voltage at which the triggercircuit will be actuated is the voltage determined by the setting of thearm of the potentiometer 118 which, together with two resistors 119 and120, forms a voltage divider. Until the voltage on the line 112 reachesthe voltage on the arm of the potentiometer 118, both transistors and116 are nonconductive, but as soon as the voltages are equal, orsubstantially so, the trigger circuit will be actuated. A firstnoisereducing capacitor 121 is connected from the emitter to the base ofthe transistor 112 and a second small noise-reducing capacitor 112 isconnected between the collector and the base of both of the transistors115 and 116.

The logic circuit that controls the operation of the circuit in FIG. 1is shown in FIG. 2. The circuit in FIG. 2 includes a NOR gate 123 with aplurality of input terminals. In the present embodiment there are twelveinput terminals, one identified by reference numeral 75 as being theoutput ter' minal of the coincidence circuit 46 in FIG. 1, and ten morewhich are the output terminals of the remaining coincidence circuits47-56. The twelfth input terminal 124 is connected to one outputterminal 125 of a flip-flop 126.

The output of the NOR gate 123 with its inverter is connected to oneinput terminal 128 of the second NOR gate 127 which has a second inputterminal 129 connected to a terminal 130, which is also shown in FIG. 1.As may be seen there, the terminal 129 is connected through anormally-open switch 131 to a positive voltage source having a value of3.6 volts, which corresponds to the high or 1 signal from the variousflip-flops in FIG. 1.

The output of the NOR gate 127 is connected through an amplifier andinverter 132 to the setting terminal 133 of a flipflop 134. Theflip-flop 134 has two output terminals 135 and 136 which are theconverse of each other; i.e. when the output voltage at the terminal 135is high, the output voltage at the output terminal 136 is low, and viceversa. The flip-flop 134 has a reset terminal 137.

The terminal 135 is connected to one input terminal 138 of a NOR gate139, while the output terminal 136-is connected to the input terminal142 of a NOR gate 144. The NOR gate 139 has two additional inputterminals 146 and 147, one of which is connected to the output terminal125 of theflip-flop 126. An amplifier and inverter 148, which isenergized from a source 149 by a signal that corresponds in durationto-the interval to be compared with the standard'interval, is connectedto the input terminal 147. The source 149 is also connected to a secondinput terminal 150 of the NOR gate l44, and the latter has a third inputterminal 151 connected to the output terminal 125 of the flip-flop 126.The output terminals of the NOR gates 139 and 144 are connected to inputterminals 152 and 153 of another NOR gate 154, which has an outputterminal 155 connected to the base input terminal of the transistor 110in FIG. 1.

The output terminal 135 of the flip-flop 134 is also connected to aninput terminal 156 of a NOR gate 157. A source 158 is connected throughan amplifier and inverter 159 to a second input terminal 160 of the NORgate 157 and the output terminal 161 of the NOR gate is connected to thereset terminal 173 of the flip-flop 126.

The operation of the circuit in FIG. 2 will be described in conjunctionwith the voltage waveforms shown in FIG. 3, and to give a more concreteinterpretation to both the circuit and the waveforms it will be assumedthat the circuit is used in conjunction with a standard injectionmolding machine (not shown) that has a piston which slides back andforth between two limit positions. When the piston slides forward itpushes a quantity of material to be molded into a die and, after havingdone so, it returns to its starting point to pick up a new quantity ofthe material. For a given type of material and a given die configurationthe speed that the piston moves forward is determined by certainconditions such as the fluidity of the material and the ability of thedies to receive it. There may be other conditions that also effect thespeed of forward movement of the piston, but in general as long as themolding process is proceeding satisfactorily each forward piston strokewill take about the same length of time. By measuring the length of timethat a forward stroke takes, a determination may be made as to whetherthe resultant molded product is likely to be satisfactory or not.

In order to get the necessary determination of stroke speed, anysuitable means, such as a pair of microswitches, may be placed alongsidethe piston to be actuated as it moves forward. One convenient way ofconnecting the switches is to cause them to produce a short voltageimpulse at the instant they are actuated by the piston. For example, thevoltage waveform 162 in FIG. 3 may be chosen to represent the actuationof a switch shortly after the beginning of piston stroke for each ofthree successive strokes. The voltage waveform 16 corresponds to theactuation of a second switch near the end of the stroke for each ofthree successive strokes, and the time between each of the pulses 162,for example pulse 162a, and the succeeding pulse from the waveform 163,which is pulse 163b, represents the time that it takes the piston tomove forward. When the machine is operating satisfactorily the timeinterval between the pulse 162a and the pulse 163k will be relativelyconstant for a large number of strokes. As conditions in the moldingprocess vary, the interval between a starting pulse 162 and aterminating pulse 163 may either lengthen or decrease.

A third pulse wave 164 is formed by the source 149 and is controlled bythe pulses 162 and 163 so that the pulses 164 are low, or in the 0condition, during the timed part of the forward stroke of the piston andhigh, or in the 1 condition from the end of the measurement of eachforward stroke until the beginning of the measurement of the nextforward stroke. The pulse wave 165 is simply the converse ofthe pulsewave 164.

While the machine is operating satisfactorily as determined byexamination of the molded products, a standard interval is memorized bymomentarily causing the switch 131 in FIG. 1 to drive the terminal 130,which appears in both FIG. 1 and 2, high. The signal at terminal 130 isindicated by reference numeral 166 and is high for a period startingbetween the pulses 163a and 162a and ending between the pulses 162a and163b. The exact timing and duration of the high signal 166 is notmaterial and in fact it could last for a total time greater than severalcomplete strokes of the machine. It could also start and end at anypoint in any cycle ofoperation of the machine.

The pulse 166 is applied to the setting input terminal 167 oftheflip-flop 126. This setting pulse causes the output terminal 125 togo high, as shown by the waveform 170 and apply a false noncoincidencesignal to the input terminal 124 of the NOR gate 123. As a result, nomatter what signals are applied to the other terminals 75, the output ofthe NOR gate 123 will remain low until theend of the measurement of thestandard interval.

The signal 166 also applies a high input via the terminal 129 to the NORgate 127 which, at this time, is receiving a low input from the NOR gate123. The high input from the signal 166 causes the output of the NORgate 127 to be low, producing an output signal 168 which is low for theduration of signal 166, as well as the duration of the high pulses 164,as will be described later. The signal 168 is inverted by the inverter132 to produce a high pulse signal 169, which is applied to the settingterminal 133 of the flip-flop 134. This causes the terminal 135 to gohigh and it remains high until the flip-flop is reset by the next pulse162 applied to the terminal 137 after the end of the signal 166. This isthe pulse 162b.

As long as the signal at the terminal 135 remains high, the output ofthe NOR gate 157 will remain low. The signal applied to the other inputterminal of the NOR gate is the pulse signal 163 inverted by theinverter 159 so that it is high except for the short duration of thepulses. However, as soon as the output of the NOR gate starts to go highdue to the pulse 1630 that denotes the end of the standard interval, theflip-flop 126 is reset and its output terminal 125 goes low, as shown inwaveform 170, which permits the output of the NOR gate 123 to go highand drive the output of the NOR gate 127 low. This signal in turn isinverted by the inverter 132 to set the flip-flop 134 and cause itsoutput terminal 135 to go high and thus to drive the output of the NORgate 157 low. As a result, the output of the NOR gate 157 may stay highfor an interval of time much shorter than the pulse 1630, as shown bythe waveform 171.

During the time the signal makes the terminal 125 high, both of theinput terminals 146 and 151 to the NOR gates 139 and 144, respectively,are high and their outputs are lowv These outputs applied to the inputterminals 152 and 153 of the NOR gate 154 cause the output terminal 155of the latter to be high. This terminal, as may be seen in FIG. 1, isconnected to the base input electrode of the transistor 110 andmaintains this transistor in a conductive state, thereby effectivelyshort circuiting the line 112 to the common terminal 111. This preventsany voltage buildup on the capacitors 77- 87 during the measurement ofthe standard interval.

The flip-flop 126 has an additional output terminal that is the converseof the terminal 125. This terminal is shown in FIG. 1 as the outputterminal of the source 29 which is connected to the NOR gate 28. Theeffect of the signal applied from the terminal 180 is to permit thepulses 14 to pass through the NOR gate 28 only when a standard intervalis being recorded. It will be recalled that these pulses are produced bythe oscillator 11. This oscillator is controlled by the signal 172 shownin FIG. 3 so that the pulses are generated only when that signal is low.This means that pulses are transmitted through the NOR gate 28 onlyduring the standard interval of time and are applied to the storageregister 32. Each pulse toggles the first flip-flop 33, and alternatepulses toggle the next flip-flop and so on down the line.

At the same time the same pulses 14 are applied to the counter-timer 16to actuate it in the same way. As long as the standard interval is beingrecorded, each of the flip-flops in the counter-timer is coincident witha corresponding flip-flop in the storage register. To be specific, thismeans that when the standard interval is being measured the outputterminal 59 of the flip-flop 17 is in the 1 condition and that when theterminal 59 reverses to the 0 condition the terminal 62 also reverses tothe 0 condition.

After the NOR gate 28 has been held open until the end of the standardinterval, it is closed and thereafter no pulses can be applied to thestorage register until the switch 131 is closed to measure-a newstandard interval. This means that whatever condition is present on theflip-flops 33-43 of the storage register 32 will remain, to serve as astandard of comparison during the measurement of subsequent intervals.On the other hand each of the flip-flops 1727 in the counter-timers isreturned to an initial condition each time one of the pulses in thewaveform 162 comes along. These pulses are applied by way of a NOR gate174 and a inverter 175 to the reset terminal of each flip-flop in thecounter-timer. This causes the counter-timer to begin a new count fromthe same initial condition at the occurrence of each of the pulses 162.

As the counter-timer counts the pulses 164 during the interval followingeach of the pulses 162 and continues until the next succeeding pulse163, the flip-flops l727 go through states of coincidence andnoncoincidence with respect to the corresponding flip-flops 33-43 of thestorage register 32. By analyzing whether there is coincidence or not,it is possible to determine whether the same time has elapsed that wasrequired to establish the condition of the flip-flops 33-43 during thestandard interval. If, at a succeeding interval of time, each of theflip-flops l727 reaches a state in which it is coincident with each ofthe flip-flops 3343, the same time must have elapsed in measuring thesubsequent interval as in measuring the standard interval.

The state of coincidence is identified by the coincidence circuits46-56, and the possibility of coincidence and noncoincidence areidentified in the following truth table for the two flip-flops 17 and 33and the coincidence circuit 46.

Non- Non- Coinei- Coinci- Coinci- Coincidencel" deuce 1 denoe0" dence0[n this table the condition identified as Coincidence 1 has been definedas that condition in which both upper terminals 59 and 62 are high, orin the 1 condition, and Coincidence 0 as that condition in which bothupper terminals are low, or in the 0 condition. Noncoincidence 1 hasbeen defined as that condition in which the terminal 59 is 0 andterminal 62 is 1 and the converse condition, Noncoincidence 0, as thatcondition in which the terminal 59 is 1 and the terminal 62 is 0.

At the start of each subsequent interval of time following the standardinterval some or all of the flip-flops 1727 will be noncoincident withcorresponding flip-flops 3343, and until sufficient time has elapsedduring the subsequent interval to allow all of the flipflops 1727 toreach a state of coincidence with the flip-flops 3343, there will alwaysbe at least one flip-flop of the counter-timer 16 that is not coincidentwith the corresponding flip-flop of the storage register 32.Noncoincidence of any pair of flip-flops results in a high signal at theoutput terminal 75 that corresponds to that pair. Thus, until completecoincidence is reached, at least one of the inputs to the NOR gate 123will be high and the condition of the setting input terminal 133 of theflip-flop 134 will be low.

Initiation of the measurement of each subsequent interval of time notonly starts the counting operation of the countertimer 16 but also isaccompanied by the occurrence of one of the pulses 162 at the resetterminal 137 of the flip-flop 134 to cause the terminal 135 to go lowand the terminal 136 to go high. The flip-flop 134 remains in thiscondition until there is complete coincidence between the counter-timer16 and the signal to the setting terminal 133 to reverse the conditionin the flip-flop 134 and drive the output terminal 135 high and theterminal 136 low.

During the measurement of the time required to reach coincidence, which,by definition, is identical with the time recorded in the storageregister, the input terminal 138 of the NOR gate 139 is low and theinput terminal 142 of the NOR gate 144 is high. As long as any input tothe NOR gate 144 is high, the output of the NOR gate, which is appliedto the input terminal 153 of the NOR gate 154 will be low.

At the same time the flip-flop 134 is reset by one of the pulse 162, thesignal 164 is applied by way of the source 149 to the input terminal 150of the NOR gate 144 and an inverted signal 165 is applied to the inputterminal 147 of the NOR gate 139. This inverted signal 165 is high atthe start of a subsequent interval of time, which causes the output ofthe NOR gate 139 to be low during the initial part of the subsequentinterval. This causes the input terminal 152 to be low initially, andsince the input terminal 153 is also low, the output terminal 155 of theNOR gate 154 is high, which is the condition required to maintain thetransistor 110 in FIG. 1 conductive. If the length of the subsequentinterval of time is exactly the same as the standard interval, the endof the low portion of waveform 164 will occur simultaneously with theestablishment of coincidence between the counter-timer 16 and thestorage register 32. As a result the signal applied to the inputterminal of the NOR gate 144 will go from low to high exactlysimultaneously with the change of the signal at the input terminal 142from high to low, and the output signal of the NOR gate 144 will remainlow. Conversely, the signal applied to the input terminal 147 will gofrom high to low at the same time that the signal applied to theterminal 138 goes from low to high, and the NOR gate 139 will thereforealso continue to apply a low signal to the input terminal 152. Thismeans that the terminal 155 will remain high as long as each subsequentinterval of time is of the same duration as the standard interval.

If a subsequent interval of time is shorter than the standard interval,the signal 164 and its inverse signal 165 will reverse polarity beforecoincidence is reached. This means that the signal applied to the inputterminal 150 will go from low to high while the signal applied to theinput terminal 142 remains high. Thus, at the instant of transition,there will be no change in the NOR gate 144, and it will continue tosupply a low signal to the input terminal 153. The reversal in polarityof the signal 165 applied to the input terminal 147 will cause thatterminal to go from high to low while the signal applied to the inputterminal 138 is still low. This means that at the instant of transitionall of the input terminals to the NOR gate 139 will be low and thereforethe output terminal of this NOR gate will be high and will apply a highsignal to the input terminal 152. This high signal will cause the outputterminal 155 to go low and drive the transistor 110 nonconductive.

As described previously, the capacitors 7787 are effectively in paralleland are related in binary terms. That is the capacitance of thecapacitor 78 is twice as large as the capacitor 77 and the capacitanceof the capacitor 79 is four times as large as that of capacitor 77, andso on. This corresponds to the fact that it takes twice as many pulses14 to reverse the polarity of the flip-flop 34 as it does to reverse thepolarity of the flip-flop 33. Whether or not the output terminal 62 ofthe flip-flop 33 is in a high or low state depends upon the number ofpulses that have been recorded in the storage register, and the samething is true of each of the other flip-flops 34-43. Some of theseflip-flops will be in one condition of conduction and others may be inthe reverse condition. If the terminal 62 is high, the transistor 88will be conductive and the capacitor 77 will be part of the chargingcircuit. The same thing is true of each of the other capacitors 7887 forwhich the corresponding transistors 89-98 are conductive. As a resultthe time constant of the charging circuit will have a specificrelationship to the standard interval of time and this relationship willchange in a binary manner with the length of the standard interval. Thusfor a longer standard interval the time constant will be larger than fora shorter standard interval. A larger time constant means that the timerequired for the active capacitors to charge to the trigger voltagelevel of the transistors 111 and 112 will be longer in proportion to thelength of the standard interval.

The waveforms associated with a subsequent interval of time shorter thanthe standard interval are shown in FIG. 3. The first waveform 176corresponds to the waveform 164 and is the signal applied to the inputterminal 150 of the NOR gate 144 in FIG. 2. As has been explained, theoutput terminal 155 of the NOR gate 254 goes low at the end of asubsequent interval of time, here identified as the low portion 176a ofthe waveform 176, unless the signal 172 goes high at the same time.Since that is not the case for a shorter-than-standard interval, asignal having a waveform 177 is produced in the output terminal 155.This signal has a low portion 177a that begins at the end of the shortinterval of time 1760 and continues until the signal 172 goes high,which occurs when all of the flip-flops 17-27 in the counter-timer 16become coincident with the flip-flops 33-43 in the storage register 32.The low signal 177a makes the transistor 110 nonconductive and allowsvoltage to build up across the operative capacitors 77- 87 to form asawtooth signal 178 as shown in FIG. 3. As this voltage crosses thetrigger voltage, indicated by the level 179, a short pulse 181 will beformed across the load impedance 117.

The operation of the system is much the same if the subsequent intervalof time is longer than the standard interval. In that case the waveformapplied to the input terminal 150 of the NOR gate 144 would be as shownin FIG. 3 by reference numeral 182. This waveform has a low portion 182athat lasts longer than the standard interval. Hence at the end of thestandard interval when the flip-flops 17-27 become coincident with theflip-flops 33-43, the output terminal 155 will be forced to go low andto stay that way until the end of the low interval 182a. This willproduce a signal 183 with a low portion 183a that operates to turn offthe transistor 110 and allow voltage to build up across the capacitors77-87. If the length of the interval 183a is longer than is permissible,the sawtooth voltage 183 built up across the operative capacitors 77-87will exceed the trigger level 179 and produce another pulse 181a acrossthe load impedance 117.

The only difference between the pulses 181 and 181a is in the intervalduring which each can occur. The pulse 181 can occur only prior tocoincidence between all the output terminals 75 because the subsequentinterval is too short, while the pulse 181a can occur only aftercoincidence has been reached because the subsequent interval is toolong.

The apparatus in FIGS. 2 and 4 includes components to make use of thepulses 181 and 1810 to produce a visual, or, if necessary, an automatic,indication that the subsequent interval oftime is not within thetolerance set by the trigger level of the transistors 115 and 116. InFIG. 2 these components include a NOR gate 186 having one input terminal187 connected to the output terminal 185 and another input terminal 188and an output terminal 189. The signal across the load impedance 117 inFIG. 1 is connected by way of an output terminal 190 and an inverter 191to the input terminal 188. A second NOR gate 193 has an input terminal194 connected to the output terminal 136 ofthe flip-flop 134 and anotherinput terminal 195 connected to the output terminal of the inverter 191.The NOR gate 193 has an output terminal 196.

In operation, a pulse 181 (or 181a) will be generated across theimpedance 117 only if the subsequent interval of time is either longeror shorter than the standard interval by more than a predeterminedpercentage of that standard interval, for

example, percent. This positive pulse is inverted in the inverter 191and applied, whenever it occurs, to the input terminals 188 and 196 as ashort, low signal. Except during the short interval represented by thepulse 181, the input terminal, 188 and 196 will be high and thereforethe output terminals 189 and 196 of the NOR gates 186 and 193,respectively, will be low. In addition, until the end of a periodequivalent to the standard interval the output terminal 136, andtherefore the input terminal 194, will also be high so that the outputterminal 196 of the NOR gate 193 cannot go high until after themeasurement of an interval equivalent to the standard interval.

At the end of an interval equivalent to the standard interval thesignals applied to the input terminals 187 and 194 reverse, andthereafter a low signal applied in the form of an instantaneous pulse tothe input terminal 188 and 196 could affect the output of the NOR gate193 but not the output ofthe NOR gate 186.

FIG. 4 shows additional circuitry-for utilizing the signal developed atthe output terminals 189 and 196 of the NOR gates 186 and 193. As may beseen, the output terminal 189 is connected to the gate electrode of asilicon-controlled rectifier, or SCR 201, which has its anode andcathode electrodes connected in series with an indicator light 202. Theoutput terminal 196 is connected to the gate electrode ofa second SCR203, which has its anode and cathode electrodes connected in series withanother indicator light 204.

The light 202 is actuated when the pulse 181 occurs and causes amomentary high signal to be applied to the terminal thereby making theSCR 201 conductive. Since this occurs only when the subsequent intervalis too short, the light 202 may be identified as the Fast light. Thelight 204 is actuated when the positive pulse 181a makes the SCR 203conductive. This can only happen when the subsequent time interval isexcessively long with respect to the standard interval, and thus thelight 204 may be identified as the Slow" light. In either case, once theSCR 201 or 203 is energized, it continues to be conductive until thecurrent through it and through the light to which it is connected isinterrupted. For this purpose a reset switch 206 is provided tointerrupt both SCR circuits momentarily in order to allow the light thatis on to go off.

As a somewhat redundant indication that the apparatus is working andthat the measured time intervals are within permissible limits, a thirdlight 208, identified as the Go" light may also be provided. This lightis connected in series with the emitter-collector circuit of atransistor 209. Current is supplied to the base of the transistor 209 bya series circuit comprising an impedance 211 and three diodes 212-214.At the junction between the impedance 211 and the diode 212 are twoother diodes 216 and connected, respectively, to the SCRs 201 and 203.

As long as there is no indication that the time interval is either tooshort or too long, the light 208 is kept on by virtue of the fact thatforward bias supplied by the impedance 211 and the diodes 212-214 keepsthe transistor 209 conductive. However, if either of the SCRs 201 or 203becomes conductive, it effectively connects the appropriate diodes 216or 217 to ground and reduces the bias on the base of the transistor 209below the conductive level. The conductive level is partly determined bythe diodes 212-214 since there is a small voltage drop across each ofthem, and connecting either the diode 216 or 217 effectively to groundreduces the voltage level at the junction between the diode 212 and theimpedance 211 below the level at which current can flow to the base ofthe transistor 209. As a result the light 208 will go off at the sametime that either the light 202 or the light 204 goes on, and it willstay off until after the reset switch 206 has been opened and closedagain.

After the apparatus has been in use for a while it may be that themachine being monitored will be switched to a different use. Forexample, if the machine is a molding machine, the dies may be changed orthe type of material being molded may change, making it necessary toreestablish a new standard interval. This requires the information beingretained in the storage register 32 in FIG. 1 to be erased, which may bedone by momentarily closing the switch 131. The latter is connectedthrough a buffer amplifier 219 to the reset terminals of all of theflip-flops 33-43. Closing the switch 129 also applies a high signal tothe NOR gate 174, which causes the output of that gate to go low andtherefore causes the output of the following inverter 175 to go high andto apply a high signal to the reset terminal 58 of the flip-flop 17 andsimilar reset terminals of all of the other flip-flops 18-27. The switch129 thus erases any stored information on all of the flip-flops l727 and3343 and returns all of them to an initial condition. Each positivepulse of the signal 162 applied to the NOR gate 174 has the same effectof returning all of the flip-flops 17- -27 to the state, but it does notaffect the setting of the flipflops 3343.

Instead of using a timing current with capacitors such as the capacitors7787 in FIG. 1 to generate the pulses 181 and 181a, another counter andanother coincidence circuit can be connected to the storage register 32of FIG. 1. The connection may be as shown in FIG. 5 in whichthe storageregister 32 may be reproduced from FIG. 1. Another counter. circuit 220comprising a series of flip-flops 221-231 identical with the flip-flops3343 is connected to a series of coincidence circuits 235-445 in exactlythe same way that the counter circuits 46-56 of FIG. I. The actual,components in the coincidence circuits 235-245. may also be identicalwith the components shown in the coincidence circuit 46 of FIG. 1. Thestorageregister 32 is connected to the coincidence circuit 235245 in thesame way that it is connected to the coincidence circuits 4656. Each ofthe coincidence circuits 235- -245 has an output terminal 248-258. Allof these output terminals are connected to corresponding input terminalsof a NOR gate 261, but the only connection which has been completed inthe drawing is that from the output terminal 258 to one of the inputterminals of the NOR gate 261. The NOR gate 261 has an output terminal262. The counter 220 is controlled by a pulse oscillator 263 which, inturn, is controlled by a gate circuit 264 that receives a signal fromthe output terminal 155 ofthe NOR gate 154 in FIG. 2.

The operation of the circuit in FIG. 5 is such that the gate 264 isclosed except when the signal applied to the input terminal 155 is low.This low signal is either the signal 177a or the signal 183a shown inFIG. 3, and the application of the low signal to the gate 264 removesthe inhibiting effect of the gate and permits the oscillator 263 togenerate a train of pulses 265. These pulses may be like the pulses 14in FIG. 1 except for having a much higher repetition rate, for example,times as high as the repetition rate of-the pulses 14.

Theapplication of these pulses to the other counting circuit 220 causesthe flip-flops 221-231 to be actuated in the same stepping succession asthe flip-flops 3343 were during the initial recording of the standardinterval. Because of the high repetition rate of the pulses 265 theflip-flops 221- 231 can reach coincidence with the flip-flops 3343 in amuch shorter time than the time required for coincidence between theflipflops l727 in FIG. 1 and the flip-flops 3343. In fact, if therepetition rate of the pulses 265 is 10 times as great as the repetitionrate of the pulses 14, the flip-flops 221-231 will reach coincidence inone-tenth the time. In general the time required to reach coincidence isl/Nth, where N is the ratio between the repetition rate of the pulses265 and the pulses 14.

If the duration of the low signal applied to the terminal 155 issufficiently long to permit all of the flip-flops 22I231 to reach astate of coincidence with the flip-flops 3343, all of the outputterminals 248258 of the coincidence circuits 235245 will go low,indicating that coincidence has been reached. Until coincidence, atleast one of these output terminals will be high and will cause theoutput of the NOR gate 261 to be low. The occurrence ofa high pulse atthe terminal 262 will be equivalent to the occurrence of either thepulse 181 or 181a of FIG. 3, and will represent the fact that thediscrepancy between the length of the subsequent interval and thestandard interval is greater than the tolerance, the tolerance beingthat fraction of the standard interval represented by the ratio of therepetition frequency of the pulses 14 to the pulses 265. If theflip-flops 221-231 continue to count beyond the point at whichcoincidence is reached, at

least one of the output terminals 248258 will gohigh again, driving theoutput of the NOR gate 261 low. Thus. coincidence will be indicated bythe presence of only a single relatively short pulse, the duration ofwhich is equal to the duration of the time between two successive onesof the pulses 265.

Iclaim:

1. A timer comprising:

a. recording means to record a standard interval of time;

b. measuring means to measure a subsequent interval of time;

0. comparison means connected to said first and second means to comparesaid subsequent interval to said standard interval;

d. first signal-generating means to generate a first signal followingthe beginning of said subsequent interval by an interval of timesubstantially equal to said standard interval;

e. second signal-generating means to generate a second signalcorresponding to the end of said subsequent interval; and

f. discrepancy measuring means connected to said recording means andsaid first and second signal-generating means to measure the interval oftime between said first and second signals as a percentage of saidstandard interval.

2. The timer of claim 1 in which said recording means comprises adigital storage register.

3. The timer of claim 2 in which said storage register comprises aseries of electronic flip-flop circuits for storing information as tothe duration of said standard interval in terms of electrical conditionsof said flip-flops.

. 4. The timer of claim I in which both of said recording means and saidmeasuring means comprise bistable circuits to store information indigitally related voltage form.

5. The timer of claim 1 comprising, in addition: a source of pulses andcircuit means connecting said source of pulses to said recording meansand to said measuring means; and control means to cause said source ofpulses to supply pulses to said recording means during said standardinterval of time and to apply said pulses to said measuring means duringsaid subsequent interval of time.

6. The timer of claim 5 in which said connecting means from said sourceof pulses to said recording means comprises from said source of pulsesto said recording means comprises a gate circuit to permit said pulsesto reach said recording means only 'while said standard interval of timeis being recorded.

7. The timer of claim 5 comprising, in addition: a second gate circuit;means to generate a control signal having a duration equal to saidstandard interval; means connecting said last-named means to said secondgate circuit to control the operation of said second gate circuit toopen said gate for a period of time equal to said standard interval; andmeans connecting said second gate circuit to said source of pulses topermit said pulses to be generated only during periods of timesubstantially equal to said standard interval.

8. The timer of claim I in which said recording means and said measuringmeans each comprises a series of electronic flip-flop circuits, eachhaving a 0 condition and a 1"condition, and said comparison meanscomprises electronic logic circuits connected to correspondingflip-flops of said recording means and said measuring means to indicateby a voltage output condition whether both of the flip-flops connectedto a particular comparison means are in the *0 condition or the 1"condition or whether one is in the 0 condition and the other is in the lcondition.

9. In the timer of claim 8 a timing circuit comprising a plurality ofcapacitors arranged in sequency whereby the capacitance of the secondcapacitor in said sequence is twice as great as the capacitance of thefirst capacitor, the capacitance of the third capacitor in said sequenceis twice as great as the capacitance of the capacitance of the secondcapacitor, and the capacitance of each subsequent capacitor in saidsequence is twice asEFat as the capacitance of the capacitor immediatelypreceding it in said sequence, a plurality of transistors, each of saidtransistors connected in series with a respective one of said capacitorsto form therewith a separate series charging circuit, and a connectionbetween between the input circuit of each of said transistors and arespective one of said flip-flops in said storage register, whereby eachof said transistors in conductive when the flipflop to which it isconnected is in its 1 condition and is nonconductive when the flip-flopto which it is connected is in its condition, whereby each of saidcapacitors connected to conductive ones of said transistors are inparallel in said timing circuit, whereby the time constant of saidtiming circuit is proportional to the duration of said standardinterval.

10. The timer of claim 9 comprising, in addition: a clamping transistorconnected in parallel with each of said series circuits and comprisingan input circuit; means to generate a pulse signal corresponding induration to the discrepancy between said staridard interval and asubsequent interval; and a connection from said last-named means to saidinput circuit of said clamping transistor to render said clampingtransistor nonconductive for the duration of said discrepancy interval.

11. In the timer of claim 8, a timing circuit comprising: a third seriesof electronic flip-flop circuits. each having a 0 condition and a 1"condition, a series of comparison logic circuits, each connected to oneflip-flop circuit of said third series and to a corresponding flip-flopcircuit of said recording means to indicate by a voltage outputcondition whether both of the flip-flops connected to a particularcomparison circuit are in the 0 condition or the 1" condition or whetherone is in the 0 condition and the other in the 1" condition; arelatively high frequency pulse source having a repetition rate N timesas great as the repetition rate of pulses of said firstnamed source;means to control the application of high frequency pulses from said highfrequency source to said third series of flip-flop circuits; and meansto indicate coincidence between all of the flip-flop circuits; and meansto indicate

1. A timer comprising: a. recording means to record a standard intervalof time; b. measuring means to measure a subsequent interval of time; c.comparison means connected to said first and second means to comparesaid subsequent interval to said standard interval; d. firstsignal-generating means to generate a first signal following thebeginning of said subsequent interval by an interval of timesubstantially equal to said standard interval; e. secondsignal-generating means to generate a second signal corresponding to theend of said subsequent interval; and f. discrepancy measuring meansconnected to said recording means and said first and secondsignal-generating means to measure the interval of time between saidfirst and second signals as a percentage of said standard interval. 2.The timer of claim 1 in which said recording means comprises a digitalstorage register.
 3. The timer of claim 2 in which said storage registercomprises a series of electronic flip-flop circuits for storinginformation as to the duration of said standard interval in terms ofelectrical conditions of said flip-flops.
 4. The timer of claim 1 inwhich both of said recording means and said measuring means comprisebistable circuits to store information in digitally related voltageform.
 5. The timer of claim 1 comprising, in addition: a source ofpulses and circuit means connecting said source of pulses to saidrecording means and to said measuring means; and control means to causesaid source of pulses to supply pulses to said recording means duringsaid standard interval of time and to apply said pulses to saidmeasuring means during said subsequent interval of time.
 6. The timer ofclaim 5 in which said connecting means from said source of pulses tosaid recording means comprises from said source of pulses to saidrecording means comprises a gate circuit to permit said pulses to reachsaid recording means only while said standard interval of time is beingrecorded.
 7. The timer of claim 5 comprising, in addition: a second gatecircuit; means to generate a control signal having a duration equal tosaid standard interval; means connecting said last-named means to saidsecond gate circuit to control the operation of said second gate circuitto open said gate for a period of time equal to said standard interval;and means connecting said second gate circuit to said source of pulsesto permit said pulses to be generated only during periods of timesubstantially equal to said standard interval.
 8. The timer of claim 1in which said recording means and said measuring means each comprises aseries of electronic flip-flop circuits, each having a ''''O''''condition and a ''''1'''' condition, and said comparison means compriseselectronic logic circuits connected to corresponding flip-flops of saidrecording means and said measuring means to indicate by a voltage outputcondition whether both of the flip-flops connected to a particularcomparison means are in the ''''0'''' condition or the ''''1''''condition or whether one is in the ''''0'''' condition and the other isin the ''''1'''' condition.
 9. In the timer of claim 8 a timing circuitcomprising a plurality of capacitors arranged in sequency whereby thecapacitance of the second capacitor in said sequence is twice as greatas the capacitance of the first capacitor, the capacitance of the thirdcapacitor in said sequence is twice as great as the capacitance of thecapacitance of the second capacitor, and the capacitance of eachsubsequent capacitor in said sequence is twice as great as thecapacitance of the capacitor immediately preceding it in said sequence,a plurality of transistors, each of said transistors connected in serieswith a respective one of said capacitors to form therewith a separateseries charging circuit, and a connection between between the inputcircuit of each of said transistors and a respective one of saidflip-flops in said storage register, whereby each of said transistors inconductive when the flip-flop to which it is connected is in its''''1'''' condition and is nonconductive when the flip-flop to which itis connected is in its ''''0'''' condition, whereby each of saidcapacitors connected to conductive ones of said transistors are inparallel in said timing circuit, whereby the time constant of saidtiming circuit is proportional to the duration of said standardinterval.
 10. The timer of claim 9 comprising, in addition: a clampingtransistor connected in parallel with each of said series circuits andcomprising an input circuit; means to generate a pulse signalcorresponding in duration to the discrepancy between said standardinterval and a subsequent interval; and a connection from saidlast-named means to said input circuit of said clamping transistor torender said clamping transistor nonconductive for the duration of saiddiscrepancy interval.
 11. In the timer of claim 8, a timing circuitcomprising: a third series of electronic flip-flop circuits, each havinga ''''0'''' condition and a ''''1'''' condition, a series of comparisonlogic circuits, each connected to one flip-flop circuit of said thirdseries and to a corresponding flip-flop circuit of said recording meansto indicate by a voltage output condition whether both of the flip-flopsconnected to a particular comparison circuit are in the ''''0''''condition or the ''''1'''' condition or whether one is in the ''''0''''condition and the other in the ''''1'''' condition; a relatively highfrequency pulse source having a repetition rate N times as great as therepetition rate of pulses of said first-named source; means to controlthe application of high frequency pulses from said high frequency sourceto said third series of flip-flop circuits; and means to indicatecoincidence between all of the flip-flop circuits; and means to indicatecoincidence between in said third series and all of the flip-flopcircuits in said recording means.